1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an element isolation region of a shallow trench isolation (STI) structure including a groove formed in one principal face of a semiconductor substrate and an insulator filled in the groove, and also to a manufacturing method of the semiconductor device.
2. Related Art
Generally, a MOS transistor having an element isolation structure such as an STI structure causes a parasitic transistor, of which the threshold voltage is lower than that of a central portion of an element region, to be easily formed at an end portion of the element region in which a gate electrode overlaps with an element isolation region. Owing to the parasitic transistor as formed, hump properties occur. The hump properties exhibit ones having deviations from the original properties of the MOS transistor, and reduce a circuit operating margin (refer to Japanese Patent Application Laid-Open (JP-A) No. 2004-288873).
In order to prevent occurrence of hump properties, the above-described patent document discloses a structure in which the gate electrode is branched off at an end portion of the element region. Due to the branched gate electrode structure being formed, a region having no gate electrode formed therein is formed at an end portion of the element region, so that a parasitic transistor is not operated in this region.
However, in a structure in which the gate electrode is branched off at the end portion of the element region as described above, a channel width becomes smaller so that current driving force is reduced, whereby there arises a problem that an element area in the channel widthwise direction would increase in order to obtain a predetermined current driving force.